Non-volatile memory (‘NVM’) devices store data even when external power supplies are disconnected. Various physical properties of materials have been proposed for data retention. The present invention relates to the kind of NVM devices in which electrical charge is retained in cells in a semiconductor device and the presence or absence of charge in a cell defines the assertion and de-assertion of a bit of data in the memory.
A particular kind of NVM device to which the invention is applicable especially, but not exclusively, is a floating gate Metal Oxide Silicon (‘MOS’) device. Such a device, as shown in FIGS. 1, 2 and 3 of the accompanying drawings comprises a floating gate 12, typically of polycrystalline Silicon, insulated from the substrate by a layer of Silicon Oxide 16 (although other insulating materials can be used) and forming a lateral Field-Effect Transistor (‘FET’) with source 18 and drain 20 regions under the face of the substrate. When writing in a cell of the memory, charge is stored in the floating gate to assert or de-assert data stored in the cell by applying an electric potential to a control gate electrode 22 connected to control gate region 24 in capacitive coupling with the floating gate 12, source 18, drain 20 and transistor region 26 being grounded and the charge tunnelling through the insulating material between the floating gate 12 on one hand and transistor region 26 on the other hand. Data is read by applying a smaller sense potential to the control gate, insufficient to cause significant amounts of charge to tunnel between the floating gate 12 on one hand and the control gate region 24 or transistor region 26 on the other hand, but such as to accumulate greater or lesser amount of charge in the channel of the transistor according to the charge stored in the floating gate 12. The data is then read by responding to the corresponding current flow between the source 18 and drain 20 of the transistor.
Data is required to be retained for a long period of time in an NVM even in the absence of an external power supply, that is to say for a period of months or years and even up to 10 years or more in some applications. A critical criterion for performance of the NVM device is that the leakage of charge from the cells must be very low, so that charge remains in the cells for the required life. This criterion is to be met by substantially all active cells in the device, even if a small proportion of individual defective cells could be tolerated if data is stored in redundant fashion and error checking algorithms are used.
Manufacturing techniques do not guarantee a sufficiently high proportion of reliable cells. Accordingly it is necessary to test the charge retention of cells in such a device for defective cells. One test technique consists of entering a known data pattern into the device, leaving the device for a period and checking whether each cell has retained the stored data. However performing this test technique at or near to room temperature requires a test time comparable with the order of magnitude of the required storage life, which is months or even years and is clearly incompatible with testing each dice of a commercial production run or even samples from each production run.
Test techniques have been proposed in attempts to accelerate obtaining the results. One such technique consists of heating the products to be tested. However, there are limits to the temperatures that can be used, in particular because heating to too high a temperature has the effect of permanently altering the physical properties of the products being tested. Furthermore heating may alter the detection of defects by annealing the material of the device under test, which may occur above approximately 125° C. with silicon semiconductor dice and this effect limits the usable temperatures. Accordingly, this technique still requires testing over periods of the order of hundreds of hours or even a thousand hours, which is still highly undesirable for testing whole production runs.
Another technique utilises the application of an electrical bias to the products to be tested to accelerate charge loss. However, it is found that the bias voltage is not effective with all cases of cells liable to charge loss, with the consequent risk of defective cells being undetected and the products shipped to customers, with corresponding degradation of production quality. Even combining the technique of heating the tested products with the application of an electrical bias does not solve the problem of quality assurance associated with the electrical bias technique, nor appreciably improve the test time for the heating technique.
Various techniques have been proposed in attempts to test other defects of semiconductor products. For example, U.S. Pat. No. 5,519,334 discloses a method of characterising charge traps in oxides using a light source. U.S. Pat. No. 6,541,987 discloses a method of laser excited detection of defective semiconductor devices. Other descriptions of test techniques appear in JEDEC standards: JESD22-A103-B August 2001“High temperature storage life” and JESD22-A117 “EEPROM Program/Erase endurance and data retention” and in the article “Evaluation of EEPROM data retention by field acceleration”, M. Lanzoni, C. Riva, P. Olivo and B. Riccó, Quality and Reliability Engineering International vo 7, 1991.
There remains a need for a reliable and rapid test for electrical charge leakage in cells in semiconductor NVM devices.